This invention relates to integrated circuit devices, and more particularly to reducing the noise in integrated circuit devices by limiting the magnitude of dI/dt variations (where dI/dt is the time gradient of current), taking into account variations in electrical parameters.
In a complex integrated circuit device such as a microprocessor chip or the like, noise generated within the device itself can become the source of false data or reduction in performance; that is, changes in current in an inductive environment result in voltage changes, as V=L(dI/dt). For example, a large number of output buffers may be simultaneously activated upon a certain system clock going high to drive external buses, and they produce a very large current surge in the power supply leads, Vdd and Vss. The rapidly-changing nature of this current surge, i.e., large time gradient of current, results in a variation in the supply voltage to the remainder of the chip due to inductance in the bond wires, pins and leads, and this variation can result in false data at sensitive nodes within the chip. To reduce this effect, it has been the practice to provide multiple power supply leads for the Vdd and Vss inputs, and to route these Vdd and Vss supplies around to various points on the chip using a number of parallel paths. This duplication of pins, bonding pads and metallization for routing of conductors utilizes excess space on the chip and increases the package cost. Another way of reducing the effect of inductive switching noise is to provide an on-chip decoupling capacitor, but this capacitance has to have a value of perhaps 10-to-100 nfd, which consumes a large amount of chip area and reduces manufacturing yield. Of course, the speed of operation of large drivers can be reduced to limit dI/dt, but this reduction would impact all process, temperature and supply variations, so the performance of the device is unduly compromised.
In U.S. Pat. No. 4,614,882, issued to Parker & May and assigned to Digital Equipment Corporation, a bus driver is disclosed which modulates the conductance of a driver transistor as a function of device parameter variations in order to optimize peak dI/dt. This circuit utilized discrete or "external" (off-chip) precision resistors, however, and so cost and space utilization were compromised.